MPSpecifications March22,2010 Revision1.0
JinglongCHIP
TheCoolest LCD Driver, Ever!
Table of Content
INTRODUCTION .................................................................................................................3 MAIN APPLICATIONS.........................................................................................................3 FEATURE HIGHLIGHTS.......................................................................................................3 ORDERING INFORMATION ..................................................................................................4 BLOCK DIAGRAM..............................................................................................................5 PIN DESCRIPTION .............................................................................................................6 RECOMMENDED COGLAYOUT..........................................................................................9 CONTROL REGISTERS.....................................................................................................10 COMMAND TABLE...........................................................................................................12 COMMAND DESCRIPTION.................................................................................................13 LCD VOLTAGESETTING..................................................................................................18 VLCD QUICK REFERENCE.................................................................................................19 LCD DISPLAYCONTROLS...............................................................................................21 ITO LAYOUT AND LCSELECTION ....................................................................................22 HOST INTERFACE............................................................................................................25 DISPLAY DATA RAM(DDRAM) ......................................................................................29 RESET & POWERMANAGEMENT......................................................................................31 ESDCONSIDERATION.....................................................................................................36 ABSOLUTE MAXIMUM RATINGS........................................................................................37 SPECIFICATIONS.............................................................................................................38 AC CHARACTERISTICS....................................................................................................39 PHYSICAL DIMENSIONS...................................................................................................43 ALIGNMENT MARK INFORMATION.....................................................................................44 PAD COORDINATES.........................................................................................................45 TRAY INFORMATION........................................................................................................47 REVISION HISTORY .........................................................................................................48
J1880x
Single-Chip, Jinglong-Low Power 65COM by 132SEG Passive Matrix LCDController-Driver
INTRODUCTION
J1880x is an advanced high-voltagemixed-signalCMOS IC,especially designed forthe display needs ofJinglong-low powerhand-held devices.
Thischip employsJinglongChip’suniqueDCC (Direct CapacitorCoupling)driver architectureto achieve nearcrosstalk freeimages.
In addition to low powercolumn and rowdrivers, the IC containsallnecessarycircuits forhigh-V LCD power supply,bias voltagegeneration, timing generation and graphicsdatamemory.
Advanced circuit design techniquesareemployed to minimize external component counts and reduceconnectorsize while achieving extremely low powerconsumption.
MAIN APPLICATIONS
. Cellular Phones, Smart Phones, PDA,and otherbattery operated palm top devicesor portable Instruments
FEATURE HIGHLIGHTS
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Single chip controller-driver support65x132 graphicsSTN LCDpanels.
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Support both row ordered andcolumn ordered displaybuffer RAMaccess.
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Support industry standard 8-bit parallelbus (8080 or 6800 mode) and 4-wire serialbus (S8)interface.
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Jinglong-low power consumption underall displaypatterns.
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Selectable MuxRate and Bias Ratioallow flexible powermanagementoptions.
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7-x internalchargepump withon-chip pumping capacitorrequires only3external capacitors to operate.
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Very low pin count(10-pin)allows exceptionalimagequality in COG formaton conventional ITO glass.
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Flexible data addressing/mappingschemes to support wide rangesofsoftwaremodels and LCD layoutplacements.
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VDD range (Typ.): 1.8V ~ 3.3V VDD2/3 range(Typ.): 2.6V ~ 3.3V LCDVOP range: 3.9V ~11.5V
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Available in gold bump dies
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COM/SEGbumpinformation Bumppitch: 27μM Bumpgap: 12μM Bumpsurface: 2077.5μM2
JINGLONGCHIP
High-Voltage Mixed-SignalIC .1999~2010
ORDERINGINFORMATION
PartNumber I2C Description
J1880xGAA No Gold Bumped Die
GeneralNotes
APPLICATION INFORMATION
For improved readability, the specification contains many application data points. When application information is given,it is advisory and does not form part of the specification for thedevice.
BARE DIEDISCLAIMER
All die are tested and are guaranteed to comply with all data sheet limits up to the point of. There is no postwaffle saw/pack testing performed on individual die. Although the latest modern processes are utilized for wafer sawing anddie pick-&-place into waffle pack carriers, JinglongChip has no control of third party procedures in the handling, packingor assembly of the die. Accordingly, it is the responsibility of the customer to test and qualify their application in which thedie is to be used. JinglongChip assumes no liability for devicefunctionality or performance of the die or systems after handling, packing or assembly of the die.
LIFESUPPORTAPPLICATIONS
These devices are not designed for use in life support appliances, or systems where malfunction of these productscan reasonably be expected to result in personal injuries. Customer using or selling these products for use insuch applications do so at their ownrisk.
CONTENT DISCLAIMER
JinglongChip believes the information contained in this document to be accurate and reliable. However, it is subject to change without notice. No responsibility is assumed by JinglongChip for its use, nor for infringement of patents or other rights ofthird parties. No part of this publication may be reproduced, or transmitted in any form or by any means without theprior consent of JinglongChip Inc. JinglongChip's terms and conditions of sale apply at alltimes.
CONTACTDETAILS
JinglongChipInc. Tel:+886(2)0755-33675536 Fax: +886 (2)0755-33675516
(Huafeng) 2F.
Sales e-mail: iawwfgiqpl@163.com Web site: http://www.szjinglong.com
BLOCK DIAGRAM
CL
JINGLONGCHIP
High-Voltage Mixed-SignalIC .1999~2010
PIN DESCRIPTION
Name Type Pins Description
MAIN POWERSUPPLY
VDD VDD2 VDD3 PWR 3 4 2 VDD supplies for Display Data RAM and digital logic, VDD2 supplies for VLCD and VD generator, VDD3 supplies for VBIAS and other analog circuits. VDD2/VDD3 should be connected to the same power source. But VDDcan be connected to a source voltage no higher thanVDD2/VDD3. Please maintain the followingrelationship: VDD+1.3V “ VDD2/3“ VDD ITO trace resistance needs to be minimized forVDD2/VDD3.
VSS VSS2 GND 2 4 Ground. Connect VSS and VSS2 to the shared GND pin. In COG applications, minimize the ITO resistance for both VSS andVSS2.
LCDPOWER SUPPLY&VOLTAGE CONTROL
VB0+ VB0– VB1+ VB1– PWR 2 2 4 2 LCD Bias Voltages. These are the voltage sources to provideSEG driving currents. These voltages are generated internally. Connect capacitors of CBX value between VBX+ and VBX–. In COG application,the resistanceof these ITO tracesdirectly affects the SEG driving strength of the resulting LCD module. Minimize thesetrace resistance is critical in achieving high qualityimage.
VLCDIN VLCDOUT PWR 2 2 Main LCD Power Supply.When VLCD is used, connect thesepins together. By-pass capacitor CL is optional. It can be connected between VLCD and VSS.When CL is used, keep the ITO trace resistance around 70~100..
NOTE
. Recommended capacitor values: CB: 2.2μF/5V or100~250x(LCD loadcapacitance).
CL: 330nF/25V is appropriate for mostapplications.
JINGLONGCHIP
High-Voltage Mixed-SignalIC .1999~2010
Name Type Pins Description
MISC.PINS
VDDX 2 Auxiliary VDD. This pin is connected to the main VDD bus within the IC. It’s provided to facilitate chip configurationsin COG application. There’s no need to connect VDDX to main VDD externally and it should NOT be used to provide VDD power to the chip.
VSSX 2 Auxiliary Vss. These pins are connected to the main Vss bus within the IC,to facilitate chip configurations in COGapplication. There’s no need to connect VssX to main Vss externally and theyshould NOT be used to provide Vss power to the chip.
TST4 I 1 Test control. There’s an on-chip pull-up resistor for TST4. Leave itopen during normaluse.
TST2 I/O 1 Test I/O pins. Leave these pins open during normaluse.
Dummy 11 Dummy pins are NOT connected inside theIC.
Note: Several controlregisters will specify “0 based index” forCOM and SEG electrodes. Inthose situations,COMx orSEGx willcorrespond to indexx-1,and the valuerange forthose indexregisterwillbe 0~63 forCOMand 0~131 forSEG.
See specifications for more
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