RM67162 DataSheet_V0.0_20160307(1).pdf
1. General Description
The RM67162 device is a single-chip solution for LTPS AMOLED that incorporates gate drivers and is
capable of 480RGBx480, 400RGBx400, 360RGBx480, 320RGBx320, 320RGBx480, 272RGBx480,
240RGBx240, 240RGBx320, 180RGBx360, 180RGBx540, 128RGBx432with internal GRAM. It includes a
5,529,600 bits internal memory, a timing controller with glass interface level-shifters and a glass power supply
circuit.
The RM67162 supports MIPI Interface, 8-bit system interfaces, serial peripheral interfaces (SPI), dual serial
peripheral interfaces (Dual-SPI). The specified window area can be updated selectively, so that moving
pictures can be displayed simultaneously independent of the still picture area.
The RM67162 is also able to make gamma correction settings separately for RGB dots to allow benign
adjustments to panel characteristics, resulting in higher display qualities. The IC possesses internal GRAM
that stores 480-RGB x 480-dot 16.77M-color images. A deep standby mode is also supported for lower power
consumption.
This LSI is suitable for wearable device applications, including I-watch and smart band.
2. Features
Single chip AMOLED controller/driver with display RAM
Display resolution option
480RGB x 480 with 480x24-bits x 480 GRAM
400RGB x 400 with 400x24-bits x 400 GRAM
360RGB x 480 with 360x24-bits x 480 GRAM
320RGB x 320 with 320x24-bits x 320 GRAM
320RGB x 480 with 320x24-bits x 480 GRAM
272RGB x 480 with 272x24-bits x 480 GRAM
240RGB x 240 with 240x24-bits x 240 GRAM
240RGB x 320 with 240x24-bits x 320 GRAM
180RGB x 360 with 180x24-bits x 360 GRAM
180RGB x 540 with 180x24-bits x 540 GRAM
128RGB x 432 with 128x24-bits x 432 GRAM
Display data RAM (frame memory): 480 x480 x 24-bits = 5,529,600 bits
Display mode (Color mode)
Full color mode: 16.7M-colors
Idle mode: 16.7M-colors, 4096-colors, 8-colors
Interface
8-bits 80-series MPU interface
Serial peripheral interface (SPI)
Dual serial peripheral interface (Dual-SPI)
MIPI Display Serial Interface (1 clock and 2 data lane pairs)
Support 1lane/2lane (1lane: 500Mbps)
Maximum total bit rate is 500Mbps of 2 data lanes 24-bit data format/ 360Mbps of 2 data
lanes 18-bit data format/ 320Mbps of 2 data lanes 16-bit data format
Abundant color display and drawing functions
Programmable γ-correction function for 16.7 million color display
Individual gamma correction setting for RGB dots
Partial display function
Sunlight readable
Control power IC by one-wire interface
On chip
VREFP5/VREFN5 voltage generator for panel voltage
VGHR/VGLR voltage for gate control signal
Internal oscillator for display clock
Source output MUX 1-6 with 240ch source output pins
Supports gate control signals to gate driver in the panel
Built-in OTP function to adjust panel setting
Logic / interface power supply voltage VDDI = 1.65V ~ 3.3V
Analog power supply voltage VDD = 2.7V ~ 3.6V
Output voltage levels
Positive gate driver voltage range for VGHR: 3 ~ 10.5V
Negative gate driver voltage range for VGLR: -2V ~ -15V
VREFP5 panel voltage range : 0~5V
VREFN5 panel voltage range : -0.5~-5V
Step-up 1,2 output voltage range for AVDD: 4.5 ~ 6.5V, VCL: -3.5 ~ -5.0V
Gamma high/low voltage range for VGMP: 2.0V ~ 6.0V (Max<=AVDD-0.5v) , VGSP: 0V, 0.3V ~ 4.5V
Package: COF/COG
Chip size evaluation : 8300um x 2360um(including scribe line)
